The present invention relates to a method of erasing a nonvolatile semiconductor storage, and more particular to a method of erasing operation of an electrically erasable and programmable read only memory (EEPROM) with a floating gate electrode.
As EEPROM types, there is a batch erasing type EEPROM (a flash type EEPROM) capable of electrically batch erasing memories of all memory cells of an array arrangement on a chip or all memory cells in a block divided from memory cell arrays on the chip.
The typical example of erasing operation of the flash type EEPROM as shown in FIG. 1 is described hereinafter. In a structure of a memory cell transistor 9, a p-type semiconductor substrate 1 is provided thereon with a composite gate 6 formed by sequentially embedding a first gate insulating film 2 composed of a silicon dioxide film of a thickness of 100 angstroms, a floating gate electrode 3, a second gate insulating film 4 composed of a composite film formed of a silicon dioxide film and a silicon nitride film of a substantial thickness of 200 angstroms and a control gate electrode 5. Further, the p-type semiconductor substrate 1 is provided thereon with a source 7 and a drain 8 respectively composed of n-type diffusion layers and electrically separated with each other with embracing the composite gate 6. As a general erasing operation, electrons are accumulated in the floating gate electrode 3 and when an erasing operation of memories of the memory cell transistor 9 written in a threshold voltage 8 V, the control gate electrode 5 is made into a ground potential, the drain 8 is made into a floating potential and the source 7 is applied with a high positive voltage, for example, 10 V for 10 miliseconds. The Fowler-Nordheim (F-N) tunnelling of electrons is performed from the floating gate electrode 3 to the source 7 through the first gate insulating film 2 so that threshold voltage of the memory cell transistor 9 is made into about 2 V. However, in such a conventional method of an erasing operation, when positive high voltage is applied to the source 7 to cause the F-N tunnelling, a surface of the source 7 under the floating gate electrode 3 is deeply depleted so as to induce the tunnelling between bands and a part of holes generated thereby is emitted into the first gate insulating film 2. Consequently, there are problems of inefficient erasing operation or a degradation of the first gate insulating film.
As an improved method of erasing of the memories to overcome the above problems, the following methods are well known. In FIG. 1, when the threshold voltage of 8 V written in the memory cell transistor 9 is made into the about 2 V in the erasing state, the p-type semiconductor substrate 1 is made into a ground potential, the source 7 and the drain 8 are made into a floating potential, and a negative high voltage - 14.5 V is applied to the control gate electrode 5 for 10 miliseconds. The F-N tunnelling of electrons accumulated in the floating gate electrode 3 is performed to the p-type semiconductor substrate 1 for an erasing operation.
According to the above method of erasing operation, on an erasing operation, tunnel current between bands is not produced on the p-type semiconductor substrate 1. Then the first gate insulating film 2 is free of deterioration. Superior repeat characteristics of a writing and an erasing operation and a characteristic free of a miss-writing may be obtained.
Notwithstanding, according to the above method of the erasing operation hereinbefore described, on the erasing operation, there is a further problem of a negative variation of the threshold voltage of the memory cell transistor because an entire portion of the first gate insulating film 2 under the floating gate electrode catches a large amount of electrons by the erasing operation and the caught electrons are slowly emitted to the side of the p-type semiconductor substrate side by a self-electric-field of the floating gate electrode. The negative variation of the threshold voltage on an erasing operation of the memory cell transistor causes an over-erasing state in which the memory cell transistor is in the depletion state.